Customer Returns Analysis
STS will verify, characterize, and perform physical and electrical failure analysis on your customer returns,
identify root cause, and develop screening and corrective action.
|QC Story/8D analysis
||Rigorous articulation of available data and
observations using industry standard quality analysis tools.
|Analyze and articulate failure signature.
||Develop detailed failure signature, assess behaviors under
electrical and environmental stresses.
|Perform manufacturing history analysis
||Evaluate manufacturing history of returns, evaluate
equipment calibration and service history context, develop
material handling biography, evaluate manufacturing relationship
of failure to historical populations.
|Electrical verification and analysis - ATE and bench flows.
||We utilizing ATE and bench electrical verification and
analysis skills to evaluate returns using our internally
developed debug and problem solving templates and work flows.
|Root cause analysis - theory articulation.
||We develop multiple theories to explain observed behaviors.
The relationship of observations and data to theories is
described. Additional data collection actions are specified to
provide support or refutation of competing theories.
|Develop containment actions.
||As soon as is practical, containment actions are articulated
and recommended to minimize customer cost and risk.
|Root cause analysis -
|We evaluate each theory in light of observations and data.
Theory based predictions are made and tested to narrow focus to
actual root cause.
|Prescribe proactive corrective actions.
||Finally, we prescribe corrective actions to be taken. When
appropriate we offer a menu of solutions including design, test,
characterization, manufacturing release and customer acceptance
methodologies to ensure elimination or reduction of DPPM loss.
Examples of customer return successes:
Periodic DPPM increases traced to manufacturing excursions
||Recommended modification of manufacturing
release and customer acceptance criteria. Articulated outgoing
QC measurements solutions. Communicated results, observations,
analysis and conclusions to manufacturing house to justify
process control improvement recommendations.
|Evaluated severe and ongoing excessive
DPPM. Systematic failure signature led to identification of
insufficient test coverage.
||Drove development, validation and integration of additional
test patterns to improve coverage. Excess DPPM eliminated.
|Excess yield loss traced to interaction
between excessive test margin specification and insufficient
||Menu of solutions developed including detailed design
modifications to increase design margin, rework of test
specification to eliminate overmargin, test hardware redesign to
improve electrical integrity and false yield loss, and process
flow options to achieve more favorable yield. Test margin
reductions were applied to recover majority of yield loss with
no subsequent DPPM increase.
|Customer qualification failures
threatened customer line-down conditions and product
introduction delay. Root cause traced to previously unidentified
process sensitivity in applied circuit topologies.
||Root cause analysis required detailed understanding of
interactions between circuit topology, process and design
methodology. Spice simulation executed by our team provided
incontrovertible evidence of root cause, further confirmed by
FIB ECO. Test screens were developed and immediately instituted
which allowed customer qualification to proceed successfully
while while final metal only ECO was instituted introduced into
production silicon build. Product release proceeded on schedule.
|Product qualification failures due to
process sensitivity were traced to inline metrology escapes.
||Root cause analysis required detailed analysis of part
handling and manufacturing history, lot travelers, lot metrology
results and correlation. Inadequate sampling technology allowed
lot excursions beyond spec in specific process parameters.
Elimination of outlier samples in qualification allowed product
qualification to complete successfully. Improvements in in-line
sampling methods eliminated future repetition of qual failure.
|Large yet intermittent systematic yield
loss traced to bad test patterns.
||Test patterns which were incorrectly testing an asynchronous
interface as though it was synchronous. New test patterns
masking bad test points were generated, eliminating periodic
yield lost with observable DPPM impact.
|Test socket wear-out caused periodic
low final test yield and subsequent COB increase.
||Simple DC parametric drift signatures were identified to
catch and replace failing sockets before yield loss was